1. Field of the Invention
The present invention relates to a content addressable memory (CAM) cell and a memory (referred to hereinafter as "FCMPLA") employing such, which is used for both a field configurable random access memory (RAM) and a programmable logic array (PLA) and has a memory configuration changeable according to a user's intention.
2. Description of the Prior Art
Recently proposed as application specific integrated circuit (ASIC) techniques have been a programmable logic device (PLD), field programmable gate array (FPGA), gate array, standard cell, custom IC design, etc..
Among them, the PLD and FPGA are programmable by the user. Recently, a field configurable memory (FCM) using a static random access memory (SRAM) has been developed for improvement in the performance of the FPGA (see: Tony Ngai, "An SRAM-Programmable Field-Configurable Memory", IEEE Custom Integrated Circuits Conference, pp 499-502, 1995).
However, the above-mentioned FCM is disadvantageous in that it cannot variously change the length of output data and has no programmable logic array function.
On the other hand, a PLA has been used for the implementation of a combinational logic circuit (may be included, for example, in a state machine) with a large number of inputs.
A CAM has been used for the implementation of a memory usable for both the PLA and RAM (see: Memory device that functions as a content addressable memory or random access memory, U.S. Pat. No. 5,408,434, 1994. 2. 3).
However, the above-mentioned memory usable for both the PLA and RAM is disadvantageous in that it has no memory configuration changeable according to a user's intention and requires a separate circuit for interconnection between blocks.
The CAM functions to compare data to be processed, with contents therein to search for a matched address, and a cell construction thereof is schematically shown in FIG. 1 herein.
With reference to FIG. 1, a conventional CAM cell 100 comprises a word line 101 which is applied with current or voltage to drive a selected word. A storage device is provided with load elements Q3 and Q4, drive elements Q1 and Q2, and access elements Q5, Q6, Q7 and Q8 constituting a transfer gate which functions as a data input/output path to the memory cell. An element Q9 is adapted to compare input data on a data line with data stored in the storage device. If the input data on the data line is the same as the data stored in the storage device, then the element Q9 is turned on. A match line 102 is operated when the element Q9 is turned on.
The operation of the CAM cell 100 with the above-mentioned construction is classified into a RAM operation as a general memory function of storing and outputting data, and a matching operation as its self-function.
A common read/write terminal must be provided in the CAM cell 100 for execution of the RAM operation of reading and writing data from/into the cell. Here, the data line is used for the data read/write operations.
The procedure of storing data in the CAM cell 100 under the condition that no data is stored therein will hereinafter be described.
First, current or voltage is applied to the word line 101 to make it high in logic, thereby causing the access elements Q5 and Q6 to be turned on. Then, if high logic input data is provided on the data line, the elements Q1 and Q4 are turned on and the elements Q2 and Q3 are turned off. As a result, a low logic value appears at a node N1 of the storage device, and a high logic value appears at a node N2 of the storage device. In this manner, the input data is stored in the CAM cell 100.
The procedure of reading data from the CAM cell 100 under the condition that a high logic value is stored at the node N2 of the storage device will hereinafter be described.
First, current or voltage is applied to the word line 101 to make it high in logic, thereby causing the access elements Q5, Q6 and Q8 to be turned on. At this time, no current flows to the element Q8 because no input data is provided on the data line. Then, the high logic value at the node N2 is transferred to the data line through the access element Q6. As a result, the high logic value at the node N2 is outputted over the data line.
The self-function or matching operation of the CAM cell 100 will hereinafter be described.
In the case where a high logic value is stored at the node N1 of the storage device, the access element Q7 remains off and the access element Q8 remains on. Under this condition, if high logic input data is provided on the data line, the element Q9 is turned on because the input data is the same as the stored data. As a result, the match line 102 is operated.
FIG. 2 shows a basic memory block which essentially comprises the CAM cells 100 with the above-mentioned construction and operation. Main input/output lines of the basic memory block are classified into three types, or a word line used for the RAM operation, a match line used for the CAM operation, and a data line used for the data input/output operations.
Interconnection circuits 200 are provided for the interconnection between basic memory blocks. As shown, each of the interconnection circuits 200 includes path transistors 202 and drivers 201. The path transistor 202 is determined in connection according to a classification and function of the associated basic memory block, which is enabled by a gate voltage.
As a result, a voltage is transferred from a cell in one basic memory block to that in the subsequent basic memory block through the electrical connection between the blocks.
The driver 201 is a circuit or amplifier which is used to remove an effect of the preceding stage. Also, the driver 201 enables the match line 102 derived from the CAM cell 100 to drive the word line 101 of the RAM. Further, the driver 201 is adapted to compensate for a voltage drop and speed reduction by the path transistor 202.
However, in the interconnection between the basic memory blocks with the conventional CAM cells, the path transistor 202 provided at the preceding stage of the driver 201 causes a voltage drop, resulting in a degradation in drive capability. Further, a large number of path transistors 202 are required.
Furthermore, the above-mentioned conventional techniques have a disadvantage in that a data width or the number of memory blocks cannot be adjusted according to a user's intention or no PLA function is present. Even though the PLA function is present, a large number of interconnection blocks must be provided, resulting in drawbacks in area and speed.